---
title: 基于FPGA的广告点阵屏（学员作品展示）
url: "https://www.fpgalearn.com/9345.html"
kind: article
id: 9345
excerpt: "verilog代码：（注意格式） `timescale 1ns / 1ps module HC_595 #( parameter SYSCLK = 50_000…"
published_at: 2025-05-27
author: 二牛学FPGA
tags: FPGA学习, FPGA工程, 学员作品, 广告屏
word_count: 1371
source: "https://www.fpgalearn.com"
---

# 基于FPGA的广告点阵屏（学员作品展示）

> 标签：FPGA学习、FPGA工程、学员作品、广告屏
> verilog代码：（注意格式） `timescale 1ns / 1ps module HC_595 #( parameter SYSCLK = 50_000…

> verilog代码：（注意格式） `timescale 1ns / 1ps module HC_595 #( parameter SYSCLK = 50_000…

![图片](https://admin.shaonianxue.cn/wp-content/uploads/2025/05/图片1-3.png)
![图片](https://admin.shaonianxue.cn/wp-content/uploads/2025/05/图片2-1.png)
![图片](https://admin.shaonianxue.cn/wp-content/uploads/2025/05/图片3-1.png)
![图片](https://admin.shaonianxue.cn/wp-content/uploads/2025/05/图片4-1.png)
verilog代码：（注意格式）
```
`timescale 1ns / 1ps
module HC_595
#(
    parameter SYSCLK = 50_000_000,//系统时钟频率
    parameter CLK_HZ = 100_000       //用系统时钟产生一个100k的频率的时钟
)
(
    input               sysclk      ,
    input               rst_n       ,
    input [15:0]        Data        ,
    input               en          ,//开始信号
    output    reg      SCK         ,
    output    reg      RCK         ,
    output    reg      DA          ,
    output    reg      Done         //结束信号
    );

localparam DELAY = SYSCLK/CLK_HZ;
localparam MID = DELAY/2;
  reg [31:0] cnt_delay;
  reg [31:0] cnt_mid;
  reg [1:0] en_temp;
  reg [15:0] data_temp;//用于存储输入进来的16bit数据
localparam IDLE = 3'b001,
           DATA = 3'b010,
           STOP = 3'b100;
  reg [2:0] cur_state,next_state;
  reg [4:0] cnt_bit;

//______________________________滤除毛刺__________________________________//
always@(posedge sysclk)
    if(!rst_n)
        en_temp = DELAY - 1 )
        cnt_delay = MID - 1 )
        cnt_mid = MID - 1)
        SCK = DELAY - 1)
                next_state = STOP;
            else
               next_state = cur_state;
        end
        STOP:begin
            if(cnt_delay >= DELAY - 1)
                next_state = IDLE;
            else
                next_state = cur_state;
        end
    endcase

//__________________________state3_________________________________//
always@(posedge sysclk)
    if(!rst_n)begin
        cnt_bit = DELAY - 1)begin
                    DA = DELAY - 1 && cnt_bit >= 5'd16)
                    cnt_bit = DELAY - 1)
                    cnt_bit = DELAY - 1)
                    Done <= 1'b1;
                else
                    Done <= 1'b0;
                cnt_bit <= 5'd0;
            end
        endcase
endmodule
```