本节课后作业：
1、请说明共阴数码管与共阳数码管。
共阳数码管： 将所有发光二极管的阳极接到一起形成共阳极(COM)的数码管，
共阴数码管：将所有发光二极管的阴极接到一起形成共阴极(COM)的数码管， 2、数码管根据发光二级管的连接方式分为哪两种数码管？
共阳数码管： 在应用时将公共极COM接到+5V, 对应段发光二极管工作时(点亮)阴极就给低电平。
共阳数码管： 在应用时将公共极COM接到地, 对应段发光二极管工作时(点亮)阳极就给高电平。
2、如果上板验证时出现问题，如何去检查问题，分几步检查？
//如果出问题：
//1.先检査程序代码
//2.检查管脚约束文件--）pin文件
//3.对应pin文件去检查实际硬件连线
//4.如果所有步骤检查后都没有问题--＞硬件是否提坏 或 板卡管脚是否损坏
`timescale 1ns / 1ps
//假设数码管位选共阳，段选共阴
//数码管静态显示四个8
///assign sel = 4'b0000;
//assign seg = 8'b0111_1111;
//数码管静态显示小练习：实现功能-->复位时，数码管显示最低位一个0；工作时，会滚动显示1~4
// 滚动显示： 最低位显示数值1，持续1s钟
// 最低两位显示数字2，持续2s
// 第三位显示数值3，持续3s
// 四位一起显示数字4，持续4s
module smg_jt(
input sysclk ,
input rst_n ,
output reg [7:0] seg ,
output reg [3:0] sel
);
parameter TIME_1s = 50_000_000 ;
reg [25:0] cnt ;
reg [4:0] cnt_sec ;
parameter IDLE = 5'b0000_1;
parameter S1 = 5'b0001_0,
S2 = 5'b0010_0,
S3 = 5'b0100_0,
S4 = 5'b1000_0;
reg [4:0] cur_state;
reg [4:0] nex_state;
always@(posedge sysclk)
if(!rst_n)
begin
cnt <= 0;
cnt_sec <= 3'd0;
end
else
if(cnt < TIME_1s -1)
cnt <= cnt + 1;
else
cnt <= 0;
always@(posedge sysclk)
if(!rst_n)
cur_state <= IDLE;
else
cur_state <= nex_state;
always@(*)
if(!rst_n)
nex_state = IDLE;
else
case(cur_state)
IDLE: nex_state = S1;
S1: if(cnt == TIME_1s-1 && cnt_sec == 3'd1)
begin
nex_state = S2;
cnt_sec = 3'd0;
end
else if (cnt == TIME_1s-1 && cnt_sec != 3'd1)
cnt_sec = cnt_sec + 1;
else
nex_state = cur_state;
S2: if(cnt == TIME_1s-1 && cnt_sec == 3'd2)
begin
nex_state = S3;
cnt_sec = 3'd0;
end
else if (cnt == TIME_1s-1 && cnt_sec != 3'd2)
cnt_sec = cnt_sec + 1;
else
nex_state = cur_state;
S3: if(cnt == TIME_1s-1 && cnt_sec == 3'd3)
begin
nex_state = S4;
cnt_sec = 3'd0;
end
else if (cnt == TIME_1s-1 && cnt_sec != 3'd3)
cnt_sec = cnt_sec + 1;
else
nex_state = cur_state;
S4: if(cnt == TIME_1s-1 && cnt_sec == 3'd4)
begin
nex_state = S1;
cnt_sec = 3'd0;
end
else if (cnt == TIME_1s-1 && cnt_sec != 3'd4)
cnt_sec = cnt_sec + 1;
else
nex_state = cur_state;
default: nex_state = IDLE;
endcase;
always@(posedge sysclk)
if(!rst_n)
begin
seg <= 8'b0000_0000;
sel <= 4'b1111;
end
else
case(cur_state)
IDLE :
begin
seg <= 8'b0011_1111;
sel <= 4'b1110;
end
S1 :
begin
seg <= 8'b0000_0110;
sel <= 4'b1110;
end
S2 :
begin
seg <= 8'b0101_1011;
sel <= 4'b1100;
end
S3 :
begin
seg <= 8'b0100_1111;
sel <= 4'b1000;
end
S4 :
begin
seg <= 8'b0110_0110;
sel <= 4'b0000;
end
default:
begin
seg <= 8'b0011_1111;
sel <= 4'b1110;
end
endcase
endmodule
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