【作业要求】 1、什么是波特率？ 单位时间内传输的码元个数 2、利用状态机编写串口接收端代码？ `timescale 1ns / 1ps module rx02( input sysclk, input rst_n, input rx, output reg [7:0] rx_data, output reg rx_done ); parameter IDLE = 4'b000_1, START …

`timescale 1ns / 1ps
module rx02(
input        sysclk,
input        rst_n,
input        rx,
output reg [7:0] rx_data,
output reg       rx_done
);
parameter   IDLE         = 4'b000_1,
START        = 4'b001_0,
W_DATA       = 4'b010_0,
STOP         = 4'b100_0,
CLK_FREQENCE = 50_000_000,
BPS          = 115200,
DELAY        = CLK_FREQENCE/BPS;
reg     [3:0]   cur_state;
reg     [3:0]   next_state;
reg rx_reg0;
reg rx_reg1;
always@(posedge sysclk or negedge rst_n)
if(!rst_n)
begin
rx_reg0 <= 1'b1;
rx_reg1 <= 1'b1;
end
else
begin
rx_reg0 <= rx;
rx_reg1 <= rx_reg0;
end
assign rx_nedge = (!rx_reg0 & rx_reg1)? 1'b1:1'b0;
always@(posedge sysclk or negedge rst_n)
if(!rst_n)
cur_state <=  IDLE;
else
cur_state <=  next_state;
reg     [31:0]  cnt_bps;
reg     [31:0]  cnt_bit;
always@(*)
if(!rst_n)
next_state = IDLE;
else
case(cur_state)
IDLE:begin
if(rx_nedge)
next_state = START;
else
next_state = IDLE;
end
START:
begin
if(cnt_bps == DELAY - 1)
next_state = W_DATA;
else
next_state = START;
end
W_DATA:
begin
if(cnt_bit == 7 && cnt_bps == DELAY - 1)
next_state = STOP;
else
next_state = W_DATA;
end
STOP:begin
if(cnt_bps == DELAY - 1)
next_state = IDLE;
else
next_state = STOP;
end
default:next_state = IDLE;
endcase
reg [7:0]  rx_data_reg;
always@(posedge sysclk or negedge rst_n)begin
if(!rst_n || cur_state == IDLE)
cnt_bps <= 0;
else if(cnt_bps == DELAY - 1)
cnt_bps <= 0;
else
cnt_bps <= cnt_bps + 1;
end
always@(posedge sysclk or negedge rst_n)begin
if(!rst_n)
cnt_bit <= 0;
else if(cur_state == W_DATA)begin
if(cnt_bps == DELAY - 1)begin
if(cnt_bit == 7)
cnt_bit <= 0;
else
cnt_bit <= cnt_bit + 1;
end
else
cnt_bit <= cnt_bit;
end
else
cnt_bit <= 0;
end
always@(posedge sysclk or negedge rst_n)begin
if(!rst_n)
rx_data_reg <= 0;
else if(cnt_bps == DELAY/2 - 1 && cur_state == W_DATA)
rx_data_reg[cnt_bit] <= rx_reg1;
else
rx_data_reg <= rx_data_reg;
end
always@(posedge sysclk or negedge rst_n)begin
if(!rst_n)
rx_data <= 0;
else if(cur_state == STOP && cnt_bps == DELAY/2 - 1)
rx_data <= rx_data_reg;
else
rx_data <= rx_data;
end
always@(posedge sysclk or negedge rst_n)begin
if(!rst_n)
rx_done <= 0;
else if(cur_state == STOP && cnt_bps == DELAY/2 - 1)
rx_done <= 1;
else
rx_done <= 0;
end
endmodule