实验报告 · 04 | 项目设计：Uart通信协议——回环测试 课程：初级 | FPGA工程师基础启航（含板卡+证书） · 第三节 基础逻辑电路设计篇 发布自课程云笔记 · FPGA 实验证据骨架 【同步·课后作业】 【作业要求】 1、什么是波特率？ 1秒钟传输的比特数量 2、利用状态机编写串口接收端代码？ `timescale 1ns / 1ps module rx( input sysclk,…

`timescale 1ns / 1ps
module rx(
input sysclk,
input rst_n,
input rx,
output reg [7:0] rx_data,
output reg rx_done
);
//状态机编码 独热码
localparam IDLE = 4'b0001;
localparam START = 4'b0010;
localparam DATA = 4'b0100;
localparam STOP = 4'b1000;
//bps定义
localparam Delay = 9'd434; //115200bps 434个时钟周期
reg [3:0] c_state;
reg [3:0] n_state;
//二级缓存
reg rx_reg0;
reg rx_reg1;
always@ (posedge sysclk or negedge rst_n)
begin
if(!rst_n)
  begin
rx_reg0 <= 1'b1;
rx_reg1 <= 1'b1;
end
else
  begin
rx_reg0 <= rx;
rx_reg1 <= rx_reg0;
end
end
wire rx_nedge;
assign rx_nedge = rx_reg1 & (~rx_reg0); //下降沿检测
//bps计数器
reg [8:0] cnt_bps;
always@ (posedge sysclk or negedge rst_n)
begin
if(!rst_n)
  begin
cnt_bps <= 9'd0;
end
else if(c_state != IDLE)
  begin
if(cnt_bps == Delay - 1)
  begin
cnt_bps <= 9'd0;
end
else
  begin
cnt_bps <= cnt_bps + 1'b1;
end
end
else
  begin
cnt_bps <= 9'd0;
end
end
//bit计数器
reg [2:0] bit_cnt;
always@ (posedge sysclk or negedge rst_n)
begin
if(!rst_n)
  begin
bit_cnt <= 3'd0;
end
else if(c_state == DATA && cnt_bps == Delay - 1)
  begin
if(bit_cnt == 3'd7)
  begin
bit_cnt <= 3'd0;
end
else
  begin
bit_cnt <= bit_cnt + 1'b1;
end
end
else
  begin
bit_cnt <= 3'd0;
end
end
//第一段---状态的跳转
always@ (posedge sysclk or negedge rst_n)
begin
if(!rst_n)
  begin
c_state <= IDLE;
end
else
  begin
c_state <= n_state;
end
end
//第二段---状态的跳转条件
always@ (*)
begin
if(!rst_n)
  begin
n_state = IDLE;
end
else
  begin
case(c_state)
IDLE:
  begin
if(rx_nedge)
  begin
n_state = START;
end
else
  begin
n_state = c_state;
end
end
START:
  begin
if(cnt_bps == Delay - 1)
  begin
n_state = DATA;
end
else
  begin
n_state = c_state;
end
end
DATA:
  begin
if(cnt_bps == Delay - 1 && bit_cnt == 3'd7)
  begin
n_state = STOP;
end
else
  begin
n_state = c_state;
end
end
STOP:
  begin
if(cnt_bps == Delay - 1)
  begin
n_state = IDLE;
end
else
  begin
n_state = c_state;
end
end
default:
  begin
n_state = IDLE;
end
endcase
end
end
//第三段---输出逻辑
reg [7:0] rx_data_reg;
always@ (posedge sysclk or negedge rst_n)
begin
if(!rst_n)
  begin
rx_data_reg <= 8'd0;
end
else
  begin
case(c_state)

rx_data_reg <= 8'd0;
end
DATA:
  begin
if(cnt_bps == Delay/2 - 1)
  begin
rx_data_reg[bit_cnt] <= rx_reg1;
end
else
  begin
rx_data_reg <= rx_data_reg;
end
end
default:
  begin
rx_data_reg <= rx_data_reg;
end
endcase
end
end
always @(posedge sysclk or negedge rst_n)
begin
if(!rst_n)
  begin
rx_data <= 8'd0;
rx_done <= 1'b0;
end
else if(c_state == STOP && cnt_bps == Delay/2 - 1)
  begin
rx_data <= rx_data_reg;
rx_done <= 1'b1;
end
else
  begin
rx_data <= rx_data;
rx_done <= 1'b0;
end
end
endmodule