【作业要求】 【我的做法】 【结果/截图说明】 module TOP( input sysclk, input rst_n, output [3:0] sel, output [7:0] seg // ); wire [13:0] number;// SMG_DT SMG_DT_u( . sysclk ( sysclk) , . rst_n ( rst_n ) , . number ( numbe…

module TOP(
input                  sysclk,
input                  rst_n,
output      [3:0]      sel,
output      [7:0]      seg      //
);
wire     [13:0]      number;//
SMG_DT SMG_DT_u(
.   sysclk   ( sysclk) ,
.   rst_n    ( rst_n ) ,
.   number   ( number) ,
.   sel      ( sel   ) ,
.   seg      ( seg   )
);
ctrl ctrl_u(
.  sysclk    ( sysclk),
.  rst_n     ( rst_n ),
.  number    ( number)/    );
endmodule
input                  sysclk,
input                  rst_n,
input       [13:0]      number,//    output   reg[3:0]      sel,
output      [7:0]      seg
);
parameter              TIME_1ms = 16'd50_000;
reg         [17:0]     cnt;
//状态声明
parameter       IDLE = 5'b0000_1,
GE   = 5'b0001_0,//
SHI  = 5'b0010_0,//
BAI  = 5'b0100_0,//
QIAN = 5'b1000_0;//
reg [4:0]  c_state,n_state;
reg [3:0]   num;        //
assign ge = number % 10;
assign shi = number /10%10;
assign bai = number /100%10;
assgin qian = number /1000;
//1ms计数器
always@(posedge sysclk)
if(!rst_n)
cnt <= 0;
else if(cnt == TIME_1ms - 1)
cnt <= 0;
else
cnt <= cnt + 1;
//
always@(posedge sysclk)
if(!rst_n)
c_state <= IDLE;
else
c_state <= n_state;
//
always@(*)
if(!rst_n)
n_state = IDLE;
else
case(c_state)
IDLE:n_state = GE;
GE  :begin
if(cnt == TIME_1ms - 1)
n_state = SHI;
else
n_state = GE;
end
SHI  :begin
if(cnt == TIME_1ms - 1)
n_state = BAI;
else
n_state = SHI;
end
BAI  :begin
if(cnt == TIME_1ms - 1)
n_state = QIAN;
else
n_state = BAI;
end
QIAN  :begin
if(cnt == TIME_1ms - 1)
n_state = GE;
else
n_state = QIAN;
end
default:n_state = IDLE;
endcase
//    always@(posedge sysclk)
if(!rst_n)
begin
sel <= 4'b0000;
num <= 0;
end
else
case(c_state)
IDLE:begin
sel <= 4'b0000;
num <= 0;
end
GE:begin
sel <= 4'b1110;
num <= ge;
end
SHI:begin
sel <= 4'b1101;
num <= shi;
end
BAI:begin
sel <= 4'b1011;
num <= bai;
end
QIAN:begin
sel <= 4'b0111;
num <= qian;
end
default:begin
sel <= 4'b0000;
num <= 8'b0011_1111;
end
endcase
YIMAQI YIMAQI_u(
.   num     (  num ),
.   seg     (  seg )
);
endmodule
input       [3:0]       num,
output   reg[7:0]       seg
);
always@(*)
case(num)//
0:seg = 8'b0011_1111;
1:seg = 8'b0000_0011;
2:seg = 8'b0011_1011;
3:seg = 8'b0100_1111;
4:seg = 8'b0110_0110;
5:seg = 8'b0110_1101;
6:seg = 8'b0111_1101;
7:seg = 8'b0000_0111;
8:seg = 8'b0111_1111;
9:seg = 8'b0110_1111;
default:seg = 8'b0011_1111;
endcase
endmodule
input               sysclk,
input               rst_n,
output  reg[13:0]   number//
);
parameter       TIME_1s = 50_000_000;
reg     [31:0]  cnt;
//1s计时器
always@(posedge sysclk)
if(!rst_n)
cnt <= 0;
else if(cnt == TIME_1s - 1)
cnt <= 0;
else
cnt <= cnt + 1;
//number数据模块
always@(posedge sysclk)
if(!rst_n)
number <= 0;
else if(cnt == TIME_1s - 1) //1s到了
begin
if(number == 5959)//                    number <= 0;
else if(number %100 == 59)//
number <= number + 41;
else
number <= number + 1;
end
else                        //1s未到
number <= number;