本节课后作业： 1、串联电阻的作用是什么？ 在FPGA 板子的Led电路中给4个led分压 2、请画出利用状态机实现1s流水灯的状态转化图并写出详细的代码。 `timescale 1ns / 1ps module led_f_fsm( input sysclk , input rst_n , output reg[3:0] led ); parameter TIME_T = 27'd50_000_…

module led_f_fsm(
input               sysclk              ,
input               rst_n               ,
output reg[3:0]     led
);
parameter           TIME_T = 27'd50_000_000;
reg [26:0]          count;
parameter           IDLE = 5'b0000_1;
parameter             S1 = 5'b0001_0,
S2 = 5'b0010_0,
S3 = 5'b0100_0,
S4 = 5'b1000_0;
reg [4:0]           cur_state;
reg [4:0]           nex_state;
reg rst_n_1;
reg rst_n_2;
always@(posedge sysclk)begin
rst_n_1 <= rst_n;
rst_n_2 <= rst_n_1;
end
always@(posedge sysclk)
if (!rst_n_2)
count <= 0;
else
if(count < TIME_T)
count <= count + 1;
else
count <= 0;
always@(posedge sysclk)
if(!rst_n_2)
cur_state <= IDLE;
else
cur_state <= nex_state;
always@(*)
if(!rst_n_2)
nex_state = IDLE;
else
case(cur_state)
IDLE: nex_state = S1;
S1:
  begin
if(count == TIME_T)
nex_state = S2;
else
nex_state = cur_state;
end
S2:
  begin
if(count == TIME_T)
nex_state = S3;
else
nex_state = cur_state;
end
S3:
  begin
if(count == TIME_T)
nex_state = S4;
else
nex_state = cur_state;
end
S4:
  begin
if(count == TIME_T)
nex_state = S1;
else
nex_state = cur_state;
end
default: nex_state = IDLE;
endcase
always@(posedge sysclk)
if(!rst_n_2)
led  <= 4'b1111;
else
case(cur_state)
IDLE    :   led <= 4'b1111;
S1    :   led <= 4'b0001;
S2    :   led <= 4'b0010;
S3    :   led <= 4'b0100;
S4    :   led <= 4'b1000;
default:    led <= 4'b1111;
endcase
endmodule