【作业要求】 1、请说明共阴数码管与共阳数码管。 共阴和共阳数码管的本质区别在于内部LED公共端的接法：共阴数码管把所有发光二极管的阴极连在一起作公共端，使用时接地，段引脚给高电平点亮；共阳数码管则把所有阳极连在一起作公共端，使用时接电源正极，段引脚给低电平点亮。 2、数码管根据发光二级管的连接方式分为哪两种数码管？ 数码管根据发光二极管的连接方式分为：共阴和共阳两种数码管。 3、如果上板验证时出…

`timescale 1ns / 1ps
//数码管静态显示小练习：实现功能-->复位时，数码管显示最低位一个0；工作时，会滚动显示1~4
// 滚动显示： 最低位显示数值1，持续1s钟
// 最低两位显示数字2，持续2s
// 第三位显示数值3，持续3s
// 四位一起显示数字4，持续4s
module smg_jt(
);
endmodule

`timescale 1ns / 1ps
/*时间单位1ns，时间精度1ps*/
module FSM_SMG(
input  wire sysclk    ,
input  wire rst_n     ,
output reg  [3:0] sel ,
output reg  [7:0] seg
);
parameter delay = 26'd50_000_000  ;
parameter  IDLE =  8'b0011_1111   ;//空闲态或者复位最后一位显示“0”
parameter    S1 =  8'b0000_0110   ,//最后一位显示“1”
S2 =  8'b0101_1011    ,//最后两位显示“2”
S3 =  8'b0100_1111    ,//最后三位显示“3”
S4 =  8'b0110_0110    ;//最后四位显示“4”
reg [27:0] count                  ;
reg [7:0]  cur_state , next_state ;//声明现次态
//1秒计数器
always @(posedge sysclk)
if(!rst_n || cur_state == IDLE)
count <= 28'b0      ;
else if ((cur_state == S1 && count ==   delay - 1)    ||
(cur_state == S2 && count ==  (delay*2) - 1) ||
(cur_state == S3 && count ==  (delay*3) - 1) ||
(cur_state == S4 && count ==  (delay*4) - 1))
count <= 28'b0        ;
else
count <= count + 28'b1 ;
//第一段描述数码管状态变化
always @(posedge sysclk)
if(!rst_n)
cur_state <= IDLE ;
else
cur_state <= next_state ;
//第二段描述各个状态之间的跳转
always @(*)
begin
if(!rst_n)
next_state = IDLE ;
else
case(cur_state)
IDLE : next_state = S1 ;
S1 :
begin
if(count == delay - 1)
next_state = S2;
else
next_state = S1;
end
S2 :
begin
if(count == (delay*2)-1)
next_state = S3;
else
next_state = S2;
end
S3 :
begin
if(count == (delay*3)-1)
next_state = S4;
else
next_state = S3;
end
S4 :
begin
if(count == (delay*4)-1)
next_state = S1;
else
next_state = S4;
end
default : next_state = IDLE ;
endcase
end
//第三段描述各个状态下的动作
always @(posedge sysclk)
if(!rst_n)begin
sel <= 4'b1110;
seg <= 8'b0011_1111;
end
else
case(cur_state)
IDLE :
begin
sel <= 4'b1110      ;
seg <= 8'b0011_1111 ;
end
S1 :
begin
sel <= 4'b1110      ;
seg <= 8'b0000_0110 ;
end
S2 :
begin
sel <= 4'b1100      ;
seg <= 8'b0101_1011 ;
end
S3 :
begin
sel <= 4'b1000      ;
seg <= 8'b0100_1111 ;
end
S4 :
begin
sel <= 4'b0000      ;
seg <= 8'b0110_0110 ;
end
default :
begin
sel <= 4'b1110      ;
seg <= 8'b0011_1111 ;
end
endcase
endmodule