【本节要点】 module key( input sysclk,input rst_n,input key,output reg led ); reg [18:0]cnt; parameter Time=50_000; always@(posedge sysclk) if (!rst_n) cnt<=0; else if (!key) begin if(cnt==Time-1) cnt<=cnt;…

module key(
input sysclk,input rst_n,input key,output reg led
);
reg [18:0]cnt;
parameter Time=50_000;
always@(posedge sysclk)
if (!rst_n)
cnt<=0;
else if (!key)
begin
if(cnt==Time-1)
cnt<=cnt;
else
cnt<=cnt+1;
end
else
cnt<=0;
assign flag=(cnt==Time-2)?1:0;
always@(posedge sysclk)
if (rst_n==0)
led<=1;
else if (flag==1)
led<=~led;
else
led<=led;