实验报告 · 08 | 项目设计：状态机设计（2） 课程：初级 | FPGA工程师基础启航（含板卡+证书） · 第二节 Verilog HDL语法篇 发布自课程云笔记 · FPGA 实验证据骨架 【本节要点】 1、串联电阻的作用是什么？ 分压 2、请画出利用状态机实现1s流水灯的状态转化图并写出详细的代码。 【我的做法】 `timescale 1ns / 1ps module LED( input…

`timescale 1ns / 1ps
module LED(
input sysclk,
input rst_n,
output reg [3:0] led
);
parameter Time_1s = 26'd50_000_000;
parameter  IDLE = 5'b0000_1,
S1 = 5'b0001_0,
S2 = 5'b0010_0,
S3 = 5'b0100_0,
S4 = 5'b1000_0;
reg [4:0] cur_state;
reg [4:0] next_state;
reg [25:0] cnt;
always @(posedge sysclk)
if (!rst_n)
cnt <= 26'd0;
else if (cnt == Time_1s -1)
cnt <= 26'd0;
else
cnt <= cnt + 1;
always @(posedge sysclk)
if (!rst_n)
cur_state <= IDLE;
else
cur_state <= next_state;
always @(*)
if(!rst_n)
next_state = IDLE;
else
case(cur_state)
IDLE: next_state = S1;
S1:
begin
if(cnt == (Time_1s - 1))
next_state  = S2;
else
next_state = cur_state;
end
S2:
begin
if(cnt == (Time_1s - 1))
next_state  = S3;
else
next_state = cur_state;
end
S3:
begin
if(cnt == (Time_1s - 1))
next_state  = S4;
else
next_state = cur_state;
end
S4:
begin
if(cnt == (Time_1s - 1))
next_state  = S1;
else
next_state = cur_state;
end
default: next_state = IDLE;
endcase
always @(posedge sysclk)
if (!rst_n)
led <= 4'b0000;
else
case(cur_state)
IDLE: led <= 4'b0000;
S1: led <= 4'b0001;
S2: led <= 4'b0010;
S3: led <= 4'b0100;
S4: led <= 4'b1000;
default: led <= 4'b1111;
endcase
endmodule